1. Field of the Invention
The invention relates to a control unit for processing modules of an integrated circuit for data processing which receives operative commands therefrom, which control unit is controlled by a clock and by an instruction generator which supplies instructions.
2. Description of the Prior Art
An integrated circuit of this kind is known from the document "A single chip, highly integrated, user programmable microcomputer", D. Stam, D. Budde and B. Morgan, Philadelphia 1977, IEEE International Solid State Circuit Conference (1977, p. 142).
Generally speaking, two parts can be distinguished in such an integrated circuit for data processing: the data processing unit and the control unit. The processing unit is formed by a plurality of operators: arithmetic operators, logic operators such as registers, combinatory logic operators (masking, extension, resetting to zero, shifting), input/output operators, etc. Each operator is defined by its function and by the time necessary for performing this function. The control unit decodes the instructions and applies the appropriate commands to the operators which then perform the operation stipulated by the instruction. The processing unit and the control unit are sequenced by a clock.
In order to define the sequencing in accordance with the present state of the art it is necessary to define the machine cycle time. This machine cycle time corresponds to the microcommand generated by the instruction for which the time required by the data to traverse the operators necessary for the execution of this microcommand is maximum. This machine cycle time is divided into a fixed number of phases, the duration of each phase amounting to a fixed number of half clock periods. Each phase validates the commands applied to a given operator by the control unit. The operators of a processing chain are thus activated in accordance with the successive phases of the machine cycle. However, such an integrated circuit for the digital processing of data has drawbacks as regards the exchange of control signals and data. This exchange is actually based on an overall sequencing of the commands. All sequencing signals for each of the operators are generated in a general fashion inside the processing unit. This multiplies the number of signals to be generated and increases the complexity of the interconnections.
The machine cycle and the phases defined to ensure an optimum performance of a processing unit also serve for the clocking of the control unit. This imposes some problems:
The phases which are useful for the processing unit must also be usable for the clocking of the control modules, necessitating different sequencing, and hence a possible degradation of the performance of the control unit. PA0 The design of the control unit is closely linked to the design of the processing unit and a modification of the sequencing of the processing unit necessitates a modification of the sequencing of the control unit. PA0 to said subsequent control module in order to ensure that its gating means prepares its control operator for the reception of said sequences of microinstructions and that each of them outputs sequences of output microinstructions to other control modules or sequences of operative commands to other processing modules, and deactivates the input semaphore at the end of the execution of each input microinstruction, PA0 or to said subsequent processing modle in order to ensure that it receives said sequences of operative commands and deactivates the input semaphore at the end of the execution of each operative command, the gating means also comprising: PA0 for informing a preceding gating means, means for deactivating their input semaphore when all subsequent control operators and all subsequent processing modules have terminated the execution of their sequences of input microinstructions or their sequences of operative commands, PA0 and, for each microinstruction issued, means for receiving validated output semaphores whose logic state has been inverted by a subsequent gating means or by a subsequent processing module, PA0 an input circuit for the input semaphore and an output validation circuit for each output semaphore, which circuits are validated by the control operator, PA0 a one-pulse generator which is activated either by activation of the input semaphore or by deactivation of the output semaphores, PA0 a phase generator which receives said pulse, supplies the necessary phases to the control operator and controls the output validation circuits and the input circuit. PA0 a sequencer which receives the input microinstructions, the input messages, and the information supplied by the memory, which sequencer determines, as a function of its inputs, the new address of the word to be read into the memory, and which generates, at the end of the execution of each input microinstruction, the end of execution signal and an output message, PA0 a memory which is clocked by the gating means, is addressed by the sequencer, supplies output microinstructions and encoded information for the sequencer, and supplies the gating means with output validation signals, PA0 a register for temporarily saving the output messages, PA0 at least one register for temporarily saving the output microinstructions, PA0 a register for temporarily saving the output messages, PA0 at least one register for temporarily saving the output microinstructions, PA0 a programmable logic array which receives the input microinstructions and the input messages and which supplies, for each input microinstruction, a sequence of output microinstructions and an output message,